The present invention refers in a general way to electronic systems for data processing and its objects include apparatus for communication of information between entities which are called processes. The concept of a process as employed in this specification is a complicated concept for although it refers to execution in sequence and in line of a series of instructions it covers both the firmware and the hardware means necessary to the execution of the sequence of instructions in question. A process is defined for the purposes of the specification and claims of the present application as the ordered execution of instructions without concurrency by either a central processor or an input/output processor. In other words, a process is the execution of a program and includes the reactions of the firmware and of the hardware to the demands of the instructions of the process.
Another object of the present invention is to enable the introduction into an information system of a trap asynchronous with the processes, that is to say, a trap such that a process A in course of execution can alert or warn a process B without the process B being put in expectation of another event. The operation known as a trap, although closely akin to an interruption is not to be confused with it. Thus an interruption enables the development of a program under way to be interrupted temporarily in order to get a program executed which is considered to have priority. More precisely the processing of an interruption generally consists, as soon as the instruction under way has finished, of safeguarding the state of the machine and then forcing into the instruction counter the address of thc first instruction associated with the interruption. This program is terminated by an instruction which restores the state of the machine at the instant at which the interruption was taken into account, which has the effect of enabling the interrupted program to be resumed. On the other hand, in a trap, the program does not return to the point at which it was interrupted, but to any point in the program which is determined by the trap.
Another object of the present invention is to define a means of communication which interrupts the process only in privilege levels inside a given level. In a system to which the invention may be applied there are defined: on the one hand, privilege levels materialized by rings (see U.S. patent application Ser. No. 528,953 filed Dec. 2, 1974, now U.S. Pat. No. 4,177,510 for "Protection for the Information in an Information Multiprocessing System Putting into Effect a Concept of Rings to Represent the Different Privilege Levels Between Processes"), and on the other hand, priority levels enabling, over a period optimum management of the operations to be carried out. As will be seen later, the number of the ring defines quantitatively the nature of the operation to be carried out. Roughly speaking the operations carried out in the zero ring are functions of the system proper which cannot in any case be interrupted since there would be a risk of no longer knowing what the state of the machine is after the interruption.
The device which is the object of the present invention takes into account the privilege level at which the operations are carried out.
A device for communication of information between processes has already been described in the U.S. patent application No. 529,015 filed Dec. 2, 1972, now U.S. Pat. No. 4,394,725, entitled "Device for Synchronization of Processes by Semaphores for an Information System". In the U.S. patent application No. 529,015, communication between the processes is ensured by means of "semaphores" which are data structures contained in the central or virtual memory and which enable a process and information necessary to this process to be associated. Two types of operations were defined in this application: operation P, during the course of which a process is a purchaser of information; and an operation V, during the course of which a process is a vendor or giver of information.
The device which is the object of the present invention enables an operation of P type to be achieved by different means. The information relative to a process is contained in the central memory in what is called a process control block PCB. A control block of this kind is described in U.S. patent application No. 528,954 filed Dec. 2, 1974 entitled "Process Control Block". The PCB information is contained in words of thirty-two bits or four octets.
In accordance with the present invention, information is communicated between two processes in a multiprogrammed information system with novel apparatus and in a novel method. The system comprises: (1) a plurality of processes, one of which is "under way" and the others of which are in the "waiting", "ready" or "suspended" state, (2) at least one central memory, and (3) one central processor (CPU) communicating with the memory. The central processor is under the command of the process which is "under way." Each process is represented in the central memory by a process control block. The multiprogrammed information system also includes an exploitation system enabling processes to be created or supressed. The novel apparatus and method are characterized in that a main word of the process control block contains a number of priority bits, preferably an octet. The priority octet is arranged so that one of its bit positions indicates whether a trap is or is not to be carried out, while one of its fields indicates in which ring numbers this trap is possible. To cause the trap, means is provided to read the bit and the field as a process passes from the ready state to the state under way.
The new elements which are characteristics of the invention are set forth in greater detail in the claims appended.